1. Field of the Invention
The present invention relates to the manufacturing of metal gate field effect transistors; more particularly to metal gate CMOS processing techniques.
2. Description of the Related Art
In conventional processes for fabricating metal gate MOS field effect transistors, the gate oxide is grown after the source and drain regions have been formed by implantation/diffusion for both the P-channel and N-channel devices. One result of this process sequence is that the source and drain regions are not self aligned with the gate. Another result is a problem known as auto-doping.
The acronym "MOS", which stands for metal-oxide-silicon, is generally used to refer to all field-effect transistors ("FETs"), including those fabricated with metal or polysilicon gates. As used herein the terms "metal gate FET", "metal gate field effect transistor", "metal gate CMOS FET", and similar terms refer to FETs having metal rather than polysilicon gates, and in which the gate oxide is formed prior to the formation of the metal gate.
The conventional process steps for fabricating metal gate CMOS field effect transistors in an N-type substrate are as follows. An initial oxide is grown on the surface of the substrate. The initial oxide is masked and etched to remove portions of the initial oxide where P-wells are to be implanted, and then P-type dopants are implanted and diffused to form the P-wells. The process of diffusing the P-wells grows a second oxide layer where the initial oxide was removed, and increases the thickness of the remaining portions of the initial oxide layer. Alternatively, the process may be performed for a P-type substrate having N-wells.
The initial oxide is then masked and etched to remove portions of the initial oxide where P.sup. -type source and drain regions are to be formed in the N-type substrate. The P-type dopant ions are introduced by implantation or vapor phase deposition, followed by a diffusion ("drive-in"). This drive-in simultaneously grows a new oxide layer in regions where the initial oxide layer was removed to allow the introduction of the P.sup. -type dopants into the substrate. The source and drain formation process is then repeated using N.sup. -type dopants to form source and drain regions in the P-wells.
After the P.sup. -type and N.sup. -type source and drain regions are formed the oxide layers are masked and etched to expose portions of the surface of the substrate corresponding to the channel regions defined between each source and drain pair. To insure that the gate oxide overlaps the source and drain regions, portions of the oxide layer overlying the portions of the source and drain regions adjacent to the channel are also removed. The gate oxide is then formed by oxidizing the substrate. After the gate oxide is grown, the oxide layers are masked and etched to open contact windows, a metal layer is deposited by sputtering, and then the metal layer is masked and etched.
Metal gate CMOS FETs fabricated using the above-described process tend to have undesirably large variations in the threshold voltages. A prime reason for variations in the threshold voltages is a phenomenon known as "auto-doping". Auto-doping is caused, in large part, by the introduction of N-type dopants into the channel regions during the oxidation process used to form the gate oxide. In particular, the heating of the wafers in the furnace used for the gate oxidation process causes diffusion of N-type dopants form the N.sup. -type source and drain regions and from the back surface of the wafer, which has an N-type background doping. In addition, the quartz furnace tubes used for the oxidation process become coated with phosphorus glass and act as a secondary source of N-type dopant ions. There may also be a transfer of P-type dopants (particularly Boron) at a less significant level.
The undesired auto-doping of the substrate under the gate oxide by with N-type dopants results in a shift of the threshold voltage in both the N-channel and P-channel FETs in a CMOS semiconductor device. The threshold voltage is a key parameter in FET operation, and thus shifts in the threshold voltage caused by auto-doping can create large differences in device performance. Further, the amount of auto-doping which occurs is related to the particular process utilized to grow the gate oxide, and even small process changes result in different threshold voltages. Accordingly, it is difficult to control the variable of the gate oxidation process to substantially eliminate auto-doping. Further, making changes in the gate oxidation process causes changes in the threshold voltage.